Design Your Chip

Showing posts with label hold timing. Show all posts

Saturday, November 24, 2012

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RTL - GDS flow

The flow chart for the GDS – RTL flow is shown below : Steps to each run viz. synthesis, PNR, STA : • Convert the pin details...
Industrial Physical Design Flow

VLSI Physical Design Flow is an algorithm with several objectives. Some of them include minimum area, wirelength and power optimization. ...
Setup and Hold checks
NEED OF MEMORY TESTING

Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandw...
Memory - RAM

The Memory of a computing system holds its state information and dominates the chip area. A memory unit (RAM) may contain millions for memor...
Good e-Books

1. Static Timing Analysis for Nanometer Designs 2. Static Timing Analysis Overview 3. High Speed and Low Power FPGA Implementation of ...
Why This Blog ?

Hi all, this is Amit Raj , from India. This blog is all about Design and Testing of Digital ICs. I don't want to treat this as only ...
ICG Enable Timing Issue

As we know Integrated Clock Gating cells are used to reduce dynamic power dissipation in the design, which is being Enable by CTRL logic. To...
ICG Optimization

In the previous post we have read about ICG Enable timing problem , to overcome the problem we use ICG optimization technique in pre-cts s...
Why Virtual Clock?

What is a virtual clock : By definition, a virtual clock is a clock without any source. Stating more clearly, a virtual clock is a clock t...

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