ICG Enable Timing Issue

As we know Integrated Clock Gating cells are used to reduce dynamic power dissipation in the design, which is being Enable by CTRL logic. To get the glitch free output from ICG cell , it should meet the timing requirement (setup/hold) at enable pin of ICG cell.

In the above figure as we seen ICG cell is driving multiple flops which is being enabled by control logic flop. suppose L2 & L3 is the latency from clock port to ICG & flops. So our ICG cell latency(latency from ICG output clock to flops) will be

                                      ICG latency = L3-L2

Ideally one ICG cell can drive infinite flops, as no. of flops going to increase driven by ICG cell,tool is going to add more buffer in the clock path to balance clock tree, which will increase the ICG latency.

As L3 latency going to increase, results in increase in ICG latency, as clock period is fixed so now we are having lesser clock period than before to meet setup timing at EN pin.

So we can conclude that Larger the ICG latency , more critical the ICG enable timing.

It is always advisable to address ICG timing in place/pre-cts stage, as after CTS it can be too late for the design to address ICG timing violation.

we know that Pre-cts timing analysis used ideal clock latency for all clock pins,that means L2=L3, & ICG latency will be 0.

As ICG latency is 0 ,which will make ICG Enable timing analysis too optimistic, because now ICG cell will get full clock to meet setup at Enable pin(before it get only L3 - ICG Latency). So, In Pre-cts actual ICG violations are not seen, therefore not fixed in the design.

To overcome this design problem ICG optimization is a technique recommended for designs having critical ICG enable timing.In the next post we will discuss about ICG optimization technique, how it is executed.