Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits.
The task of testing a VLSI chip to guarantee its functionality is extremely complex and often very time consuming. In addition to the problem of testing the chips themselves, the incorporation of the chips into systems has caused test generation’s cost to grow exponentially.
a) Memory testing is an extremely important issue owing to a host of reasons. RAMs are the key components for electronic systems. Memories represent about 30% of the semiconductor market. Embedded memories are dominating the chip yield these days.
b) Memory testing is becoming highly difficult due to growing density, capacity, and speed.
c) New architectures and technologies are emerging at a fast pace. Embedded memories require certain factors to be looked after such as diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc.
d) Cost of memory testing drives the need for more efficient test methodologies. Few of the techniques already in use are IFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.
Test automation is required. It calls for failure analysis, fault simulation, ATG, and diagnostics and BIST/BIRA/BISR generation.
