Good e-Books

1. Static Timing Analysis for Nanometer Designs 

2. Static Timing Analysis Overview

3. High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications

4.  Essential VHDL

5. Transistors Tutorial 

6. Op Amp (741) Tutorial 

7. Capacitor Tutorial

 

NEED OF MEMORY TESTING

Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits.

The task of testing a VLSI chip to guarantee its functionality is extremely complex and often very time consuming. In addition to the problem of testing the chips themselves, the incorporation of the chips into systems has caused test generation’s cost to grow exponentially.

a) Memory testing is an extremely important issue owing to a host of reasons. RAMs are the key components for electronic systems. Memories represent about 30% of the semiconductor market. Embedded memories are dominating the chip yield these days. 

b) Memory testing is becoming highly difficult due to growing density, capacity, and speed. 

c) New architectures and technologies are emerging at a fast pace. Embedded memories   require certain factors to be looked after such as diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc. 

d) Cost of memory testing drives the need for more efficient test methodologies. Few of the techniques already in use are IFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.

 

Test automation is required. It calls for failure analysis, fault simulation, ATG, and diagnostics and BIST/BIRA/BISR generation.

Memory - RAM

The Memory of a computing system holds its state information and dominates the chip area. A memory unit (RAM) may contain millions for memory addressable cells. Memory cells are organized into arrays wherein each cell is addressable by a row address and a column address. Memories are the most defect sensitive components as they are fabricated with minimal feature widths. It highly raises the total chip DPM (Defects Per Million) level and thus, calls for high quality tests and repair.

6-transistors SRAM cell

 

RAM Organization

Why This Blog ?

Hi all, this is Amit Raj, from India.

This blog is all about Design and Testing of Digital ICs. I don't want to treat this as only a blog, but a forum, where we can discuss anything but about VLSI.
It can be Verilog - RTL Coding, or Basics of IC Design, or Timing, Placement and Routing, LEC, STA, DFT.

Please feel free to leave any comments or send any new comments to the author for putting here..